If it's for a single prototype, just use the biggest FPGA you can afford. four families that are optimized for specific capabilities: Spartan-6 FPGAs for I/O optimization. But given 2-inputs, there’s lots of possible output combinations, which all must be possible to satisfy given a 2-input LUT. FPGA, 6-input LUT, SRAM Ultra Family : FPGA, 6. The above examples show a 2-input LUT that has been configured to be an AND gate and an OR gate. I suggest you choose your vendor, port enough of your design to get an idea of how big a FPGA you need and choose a FPGA with an upgrade path (if you want to market). A Look-Up Table (LUT) is how any arbitrary Boolean logic gets implemented inside your FPGA. The same design on two different foundries should have similar system gates number, as waste is not really an issue for ASIC. System gates is a common measure of ASIC design complexity. Same with fast-carry logic, I don't know if they count that in equivalent gate number, but be advised that number is inflated. Although mainstream FPGAs typically use 6-input LUTs, this example illustrates a 3-input LUT for simplicity but the principle of operation is the same. 46 Detailed schematic of a standard fracturable 6-input LUT. A Xilinx FPGA should fit 1.5 times the logic of an Altera FPGA, since it's LUT have 6 instead of 4, right? Well, it largely depends on the design, if the design can't use 6-inputs much, the unused ones are wasted. 6 Improved Example: 6,2 Fracturable LE 8 Inputs, 2 outputs, 2 registers 1 6LUT 2 5LUTs with input Sharing 2 independent 4 LUTS comparable in area with two. 46 illustrates the detailed schematic of a standard fracturable 6-input LUT, where the 5th and 6th inputs can be pull up/down to a fixed logic value to enable LUT4 and LUT5 outputs. ![]() They are aggregated in logic blocks which has other features like fast-carry chain, registers and distributed memory.Ĭonverting to system gates is useful, but don't forget it's also a marketing war. To give a simple example, if you want to implement a 61 mux, you can use a 6-input LUT or two 4-input LUTs. ![]() In their most recent architecture, Xilinx use 6-input LUT and altera 4-input LUT. Xilinx use LUT, Altera LE, microsemi/lattice possibly something else. LUT, Logic Cell and Logic Element are all the same to me: the most basic FPGA general logic primitive. Therefore, a LUT will typically implement the equivalent of multiple 2-input gates the complexity of the function doesn’t matter at all.
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